Study of nitridation plasma for ultra-thin gate dielectrics of 65 nm technology node and beyond

被引:0
|
作者
Wu, HM [1 ]
Gao, D [1 ]
Mo, MX [1 ]
Zhou, N [1 ]
Chen, J [1 ]
Zhu, B [1 ]
Ning, J [1 ]
Bonfanti, P [1 ]
Kuo, J [1 ]
Li, M [1 ]
机构
[1] Semicond Mfg Corp, LTDM, Shanghai, Peoples R China
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the present paper, to find the effective optimization of operation parameters in manufacturing, the gate dielectric nitridation in high-density plasma has been systematically studied by both theoretical and experimental methods. The experimental data are validated against the modeling results. Some plasma parameter correlation has been established to provide a guideline to optimize the nitridation profile in gate dielectric layer across wafer. It paves a way to make further improvement of device performance.
引用
收藏
页码:415 / 418
页数:4
相关论文
共 50 条
  • [41] Novel fabrication process to realize ultra-thin (EOT=0.7nm) and ultra-low leakage SiON gate dielectrics
    Matsushita, D
    Muraoka, K
    Nakasaki, Y
    Kato, K
    Inumiya, S
    Eguchi, K
    Takayanagi, M
    2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2004, : 172 - 173
  • [42] SILC during NBTI stress in PMOSFETs with ultra-thin SiON gate dielectrics
    Cao, Yan-Rong
    Hao, Yue
    Ma, Xiao-Hua
    Yu, Lei
    Hu, Shi-Gang
    CHINESE PHYSICS LETTERS, 2008, 25 (04) : 1427 - 1430
  • [43] Reliability challenges of high performance PD SOICMOS with ultra-thin gate dielectrics
    Zhao, E
    Zhang, J
    Salman, A
    Subba, N
    Chan, J
    Marathe, A
    Beebe, S
    Taylor, K
    SOLID-STATE ELECTRONICS, 2004, 48 (10-11) : 1703 - 1708
  • [44] Advantage of the structure and the electrical properties of epitaxial ultra-thin zirconia gate dielectrics
    Kiguchi, Takanori
    Wakiya, Naoki
    Tanaka, Junzo
    Shinozaki, Kazuo
    MATERIALS SCIENCE AND ENGINEERING B-ADVANCED FUNCTIONAL SOLID-STATE MATERIALS, 2008, 148 (1-3): : 30 - 34
  • [45] Optical metrology for ultra-thin oxide and high-K gate dielectrics
    Chism, WW
    Diebold, AC
    Price, J
    CHARACTERIZATION AND METROLOGY FOR ULSI TECHNOLOGY, 2003, 683 : 124 - 128
  • [46] Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics
    Tsujikawa, S
    Mine, T
    Watanabe, K
    Shimamoto, Y
    Tsuchiya, R
    Ohnishi, K
    Onai, T
    Yugami, J
    Kimura, S
    41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2003, : 183 - 188
  • [47] Voltage acceleration of time-dependent breakdown of ultra-thin gate dielectrics
    Pompl, T
    Röhner, M
    MICROELECTRONICS RELIABILITY, 2005, 45 (12) : 1835 - 1841
  • [48] Ultra-thin gate oxide technology for high performance CMOS
    Momose, HS
    Nakamura, S
    Katsumata, Y
    Iwai, H
    ULSI SCIENCE AND TECHNOLOGY / 1997: PROCEEDINGS OF THE SIXTH INTERNATIONAL SYMPOSIUM ON ULTRALARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY, 1997, 1997 (03): : 235 - 246
  • [49] Mask inspection technology for 65nm (hp) technology node and beyond
    Tojo, T
    Hirano, R
    Inoue, H
    Imai, S
    Yoshioka, N
    Ohira, K
    Chung, DH
    Terasawa, T
    Characterization and Metrology for ULSI Technology 2005, 2005, 788 : 457 - 467
  • [50] Plasma-charging damage in ultra-thin gate oxide
    Cheung, KP
    MICROELECTRONICS RELIABILITY, 2000, 40 (12) : 1981 - 1986