Study of nitridation plasma for ultra-thin gate dielectrics of 65 nm technology node and beyond

被引：0

作者：

Wu, HM ^{[1
]}

Gao, D ^{[1
]}

Mo, MX ^{[1
]}

Zhou, N ^{[1
]}

Chen, J ^{[1
]}

Zhu, B ^{[1
]}

Ning, J ^{[1
]}

Bonfanti, P ^{[1
]}

Kuo, J ^{[1
]}

Li, M ^{[1
]}

机构：

[1] Semicond Mfg Corp, LTDM, Shanghai, Peoples R China

来源：

2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In the present paper, to find the effective optimization of operation parameters in manufacturing, the gate dielectric nitridation in high-density plasma has been systematically studied by both theoretical and experimental methods. The experimental data are validated against the modeling results. Some plasma parameter correlation has been established to provide a guideline to optimize the nitridation profile in gate dielectric layer across wafer. It paves a way to make further improvement of device performance.

引用

页码：415 / 418

页数：4

共 50 条

[11] Study on Mechanism of Thermal Curing in Ultra-thin Gate Dielectrics
Mitani, Yuichiro
Higashi, Yusuke
Nakasaki, Yasushi
2018 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2018,
[12] Study on ultra-thin gate dielectrics: Surface preparation and reliability
Jia, L
Chai, SM
Xu, QX
Qian, H
1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS, 1998, : 120 - 122
[13] Effects of plasma nitridation on ultra-thin gate oxide electrical and reliability characteristics
He, YD
Xu, MZ
Tan, CH
SOLID-STATE ELECTRONICS, 2005, 49 (01) : 57 - 61
[14] Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm General Purpose CMOS applications
Veloso, A
Cubaynes, FN
Rothschild, A
Mertens, S
Degraeve, R
O'Connor, R
Olsen, C
Date, L
Schaekers, M
Dachs, C
Jurczak, M
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 239 - 242
[15] He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications
Ting, SF
Fang, YK
Chen, CH
Yang, CW
Yu, MC
Jang, SM
Yu, CH
Liang, MS
Chen, SW
Shih, R
ELECTRONICS LETTERS, 2001, 37 (12) : 788 - 790
[16] Ultra-thin gate oxide lifetime projection and degradation mechanism beyond 90 nm CMOS technology
Lin, Cheng-Li
Kao, Tom
Chen, Ju-Ping
Yang, Jeff Y. C.
Su, K. C.
2006 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT, 2006, : 186 - +
[17] Effects of post-decoupled-plasma-nitridation annealing of ultra-thin gate oxide
Lek, CM
Cho, BJ
Loh, WY
Ang, CH
Lin, W
Tan, YL
Zhen, JZ
Chan, L
Tan, SS
Chen, TP
PROCEEDINGS OF THE 9TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2002, : 232 - 236
[18] RECENT DEVELOPMENTS IN ULTRA-THIN OXYNITRIDE GATE DIELECTRICS
HAN, LK
BHAT, M
WRISTERS, D
WANG, HH
KWONG, DL
MICROELECTRONIC ENGINEERING, 1995, 28 (1-4) : 89 - 96
[19] Investigation of ultra thin thermal nitrided gate dielectrics in comparison to plasma nitrided gate dielectrics for high-performance logic application for 65nm
AMD Fab36 LLC and Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany
不详
Mater Sci Forum, 2008, (153-163):
[20] Inelastic Electron Tunneling Spectroscopy (IETS) Study of Ultra-thin Gate Dielectrics for Advanced CMOS Technology
Ma, T. P.
SILICON NITRIDE, SILICON DIOXIDE, AND EMERGING DIELECTRICS 11, 2011, 35 (04): : 545 - 561

← 1 2 3 4 5 →