Study of nitridation plasma for ultra-thin gate dielectrics of 65 nm technology node and beyond

被引:0
|
作者
Wu, HM [1 ]
Gao, D [1 ]
Mo, MX [1 ]
Zhou, N [1 ]
Chen, J [1 ]
Zhu, B [1 ]
Ning, J [1 ]
Bonfanti, P [1 ]
Kuo, J [1 ]
Li, M [1 ]
机构
[1] Semicond Mfg Corp, LTDM, Shanghai, Peoples R China
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the present paper, to find the effective optimization of operation parameters in manufacturing, the gate dielectric nitridation in high-density plasma has been systematically studied by both theoretical and experimental methods. The experimental data are validated against the modeling results. Some plasma parameter correlation has been established to provide a guideline to optimize the nitridation profile in gate dielectric layer across wafer. It paves a way to make further improvement of device performance.
引用
收藏
页码:415 / 418
页数:4
相关论文
共 50 条
  • [2] Process optimization of plasma nitridation SiON for 65 nm node gate dielectrics
    He YanDong
    Zhang Xing
    Wang YangYuan
    SCIENCE CHINA-INFORMATION SCIENCES, 2011, 54 (12) : 2673 - 2679
  • [3] Process optimization of plasma nitridation SiON for 65 nm node gate dielectrics
    YanDong He
    Xing Zhang
    YangYuan Wang
    Science China Information Sciences, 2011, 54 : 2673 - 2679
  • [4] Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology
    Tseng, HH
    Jeon, Y
    Abramowitz, P
    Luo, TY
    Hebert, L
    Lee, JJ
    Jiang, J
    Tobin, PJ
    Yeap, GCF
    Moosa, M
    Alvis, J
    Anderson, SGH
    Cave, N
    Chua, TC
    Hegedus, A
    Miner, G
    Jeon, J
    Sultan, A
    IEEE ELECTRON DEVICE LETTERS, 2002, 23 (12) : 704 - 706
  • [5] Electrical characteristics and reliability of ultra-thin gate oxides (<2nm) with plasma nitridation
    Sun, Ling
    Liu, Wei
    Duan, Zhenyong
    Xu, Zhongyi
    Yang, Huayue
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2008, 29 (11): : 2143 - 2147
  • [6] Plasma nitridation of very thin gate dielectrics
    Al-Shareef, HN
    Bersuker, G
    Lim, C
    Murto, R
    Borthakur, S
    Brown, GA
    Huff, HR
    MICROELECTRONIC ENGINEERING, 2001, 59 (1-4) : 317 - 322
  • [7] Ultra-thin oxynitride gate dielectrics for 0.18 μm CMOS and beyond
    Takayanagi, Mariko
    Toyoshima, Yoshiaki
    International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings, 1999,
  • [8] Ultra-Thin SOI for 20nm node and beyond
    Aulnette, C.
    Schwarzenbach, W.
    Daval, N.
    Bonnin, O.
    Nguyen, B-Y
    Mazure, C.
    Maleville, C.
    Cheng, K.
    Ponoth, S.
    Khakifirooz, A.
    Hook, T.
    Doris, B.
    2011 IEEE INTERNATIONAL SOI CONFERENCE, 2011,
  • [9] Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics
    Inaba, S
    Shimizu, T
    Mori, S
    Sekine, K
    Saki, K
    Suto, H
    Fukui, H
    Nagamine, M
    Fujiwara, M
    Yamamoto, T
    Takayanagi, M
    Mizushima, I
    Okano, K
    Matsuda, S
    Oyamatsu, H
    Tsunashima, Y
    Yamada, S
    Toyoshima, Y
    Ishiuchi, H
    INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 651 - 654
  • [10] Evaluation of silicon surface nitridation effects on ultra-thin ZrO2 gate dielectrics
    Nieh, R
    Choi, R
    Gopalan, S
    Onishi, K
    Kang, CS
    Cho, HJ
    Krishnan, S
    Lee, JC
    APPLIED PHYSICS LETTERS, 2002, 81 (09) : 1663 - 1665