Intrinsic leakage in deep submicron CMOS ICs - Measurement-based test solutions

被引：29

作者：

Keshavarzi, A ^{[1
]}

Roy, K

Hawkins, CF

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

[2] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA

[3] Univ New Mexico, Dept Elect & Comp Engn, Albuquerque, NM 87131 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2000年 / 8卷 / 06期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/92.902266

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The high leakage current in deep submicron, short-channel transistors call increase the stand-by power dissipation of future IC products and threaten well established quiescent current (I-DDQ)-based testing techniques. This paper reviews transistor intrinsic leakage mechanisms. Then, these well-known device properties are applied to a test application that combines I-DDQ and ICs maximum operating frequency (F-max) to establish a novel two-parameter test technique for distinguishing intrinsic and extrinsic (defect) leakages in ICs with high background leakage. Results show that I-DDQ along with F-max can be effectively used to screen defects in high performance, low V-T (transistor threshold voltage) CMOS ICs.

引用

页码：717 / 723

页数：7

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