Intrinsic leakage in deep submicron CMOS ICs - Measurement-based test solutions

The high leakage current in deep submicron, short-channel transistors call increase the stand-by power dissipation of future IC products and threaten well established quiescent current (I-DDQ)-based testing techniques. This paper reviews transistor intrinsic leakage mechanisms. Then, these well-known device properties are applied to a test application that combines I-DDQ and ICs maximum operating frequency (F-max) to establish a novel two-parameter test technique for distinguishing intrinsic and extrinsic (defect) leakages in ICs with high background leakage. Results show that I-DDQ along with F-max can be effectively used to screen defects in high performance, low V-T (transistor threshold voltage) CMOS ICs.