A CORDIC-based unified systolic architecture for sliding window applications of discrete transforms

被引：11

作者：

Kar, DC ^{[1
]}

Rao, VVB ^{[1
]}

机构：

[1] N DAKOTA STATE UNIV,DEPT ELECT ENGN,FARGO,ND 58105

来源：

IEEE TRANSACTIONS ON SIGNAL PROCESSING | 1996年 / 44卷 / 02期

关键词：

D O I：

10.1109/78.485943

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CORDIC-based, unified systolic architecture for sliding window applications of the discrete Fourier transform (DFT), the discrete Hartley transform (DHT), the discrete cosine transform (DCT), and the discrete sine transform (DST) is proposed. Compared to earlier works, the proposed scheme offers significant reduction in hardware, particularly for DHT. For an N-point DHT, it requires only right perpendicular N/2 left perpendicular + 1 processing elements, each consisting of one CORDIC processor and two adders.

引用

页码：441 / 444

页数：4

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