On Supporting Sequential Constraints for On-Chip Generation of Post-Silicon Validation Stimuli

被引：3
|
作者：
Shi, Xiaobing [1 ]
Nicolici, Nicola [1 ]
机构：
[1] McMaster Univ, Dept Elect & Comp Engn, Hamilton, ON, Canada
来源：
2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS) | 2014年
关键词：
D O I：
10.1109/ATS.2014.30
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of functionally-compliant randomized sequences with support for sequential constraints.
引用
收藏
页码：107 / 112
页数：6
相关论文
共 50 条
  • [1] On-Chip Stimuli Generation for Post-Silicon Validation
    Nicolici, Nicola
    2012 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2012, : 108 - 109
  • [2] On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation
    Shi, Xiaobing
    Nicolici, Nicola
    2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2015, : 808 - 815
  • [3] On-Chip Constrained Random Stimuli Generation for Post-Silicon Validation Using Compact Masks
    Shi, Xiaobing
    Nicolici, Nicola
    2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2014,
  • [4] On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation
    Shi, Xiaobing
    Nicolici, Nicola
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (06) : 1012 - 1025
  • [5] In-System Constrained-Random Stimuli Generation for Post-Silicon Validation
    Kinsman, Adam B.
    Ko, Ho Fai
    Nicolici, Nicola
    PROCEEDINGS INTERNATIONAL TEST CONFERENCE 2012, 2012,
  • [6] Enhancing Observability for Post-Silicon Debug with On-Chip Communication Monitors
    Cao, Yuting
    Palombo, Hernan
    Zheng, Hao
    Ray, Sandip
    2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018, : 602 - 607
  • [7] Concurrent Generation of Concurrent Programs for Post-Silicon Validation
    Adir, Allon
    Nahir, Amir
    Ziv, Avi
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2012, 31 (08) : 1297 - 1302
  • [8] On automated trigger event generation in post-silicon validation
    Ko, Ho Fai
    Nicolici, Nicola
    2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1328 - 1331
  • [9] On-chip Dynamic Signal Sequence Slicing for Efficient Post-Silicon Debugging
    Lee, Yeonbok
    Matsumoto, Takeshi
    Fujita, Masahiro
    2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
  • [10] An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time
    Oh, Hyunggoy
    Han, Taewoo
    Choi, Inhyuk
    Kang, Sungho
    IEEE TRANSACTIONS ON COMPUTERS, 2017, 66 (01) : 38 - 44
12345