A Flipped Voltage Follower Based Analog Multiplier In 90nm CMOS Process

被引：0

作者：

Satapathy, Amarjyoti ^{[1
]}

Maity, Subir Kumar ^{[1
]}

Mandal, Sushanta K. ^{[2
]}

机构：

[1] KIIT Univ, Sch Elect Engn, Bhubaneswar 751024, Orissa, India

[2] NIST, VLSI Res Grp, Berhampur, Odisha, India

来源：

2015 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER ENGINEERING AND APPLICATIONS (ICACEA) | 2015年

关键词：

Amplitude Modulation; Analog Multiplier; Flipped Voltage Follower; Low voltage design technique; Source Follower;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper, a five transistor voltage adder, consisting of a flipped voltage follower devised to work in low voltage rail, has been used as the main building block for designing an analog multiplier. Four of such cells have been used for biasing and signaling. This Multiplier has been designed using GPDK 90nm CMOS technology and simulated in Cadence Spectre environment. The supply voltage has been taken as 1-Volt. In worst case the multiplier consumes 178 mu W power and perfectly working up to 454.56 MHz with less than 1.5% harmonic distortion components.

引用

页码：628 / 631

页数：4

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