Linear transconductor with flipped voltage follower in 130 nm CMOS

被引：4
|
作者：
Ajayan, K. R. [1 ]
Bhat, Navakanta [1 ]
机构：
[1] Indian Inst Sci, Dept Elect Commun Engn, Bangalore 560012, Karnataka, India
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2010年 / 63卷 / 02期
关键词：
CMOS analog circuits; Threshold voltage variability; Flipped voltage follower; Adaptive biasing; Linear transconductor; DESIGN; CIRCUIT;
D O I：
10.1007/s10470-009-9396-5
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.
引用
收藏
页码：321 / 327
页数：7
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