Modulo-(2n-2q-1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues

The residue number system tau = {2(n) - 1, 2(n), 2(n) + 1} has been extensively studied towards perfection in realization of efficient parallel prefix modular adders, with (3 + 2logn Delta G latency. Many applications, such as digital signal processing require fast modular operations. However, relying only on tau limits the magnitude of n, and accordingly the dynamic range. Therefore, additional mutually prime moduli are required to accommodate for wider dynamic range. On the other hand, speed of modular arithmetic operations for the additional moduli should be as close as possible to those in tau. This could be best met by the moduli of the form 2"- (2q + 1), with 1 <= q <= n - 2, such as 2(n) - 3, 2(n) - 5. However, the fastest parallel prefix realization of modulo-(2(n) - 2(q)- 1) adders that we have encountered in the relevant literature, claims (7 + 2 log n)Delta G latency. Motivated by the need to reduce the latter, we propose new designs of such adders with (5 + 2 log n)Delta G latency without any penalty in area consumption or power dissipation. The proposed modular addition algorithm entails supplementary representation of residues in [0, 2(q), as [2(n) - (2(q) + 1), 2(n) - 1]. This leads to additional performance efficiency similar to the effect of double zero representation in modulo-(2(n) - 1) adders. The aforementioned analytically evaluated speed gain and improvements in other figures of merit are also supported via circuit simulation and synthesis.