共 50 条
- [1] Enhanced model based OPC for 65nm and below [J]. 24TH ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PT 1 AND 2, 2004, 5567 : 1305 - 1314
- [2] Performance Enhanced Op-Amp for 65nm CMOS Technologies and Below [J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 201 - 204
- [3] Phenomena and OPC solution of ripple patterns for 65nm node [J]. OPTICAL MICROLITHOGRAPHY XVII, PTS 1-3, 2004, 5377 : 1165 - 1171
- [4] Combining OPC and design for printability into 65nm logic designs [J]. DESIGN AND PROCESS INTEGRATION FOR MICROELECTRONIC MANUFACTURING II, 2004, 5379 : 158 - 169
- [5] A new category of particles at 65nm technology and below [J]. 2006 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP, 2006, : 380 - 382
- [6] 65nm OPC and design optimization by using simple electrical transistor simulation [J]. DESIGN AND PROCESS INTEGRATION FOR MICROELECTRONIC MANUFACTURING III, 2005, 5756 : 378 - 388
- [7] An integrated solution for photomask manufacturing, handling and storage at 65nm and below [J]. METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XX, PTS 1 AND 2, 2006, 6152
- [8] Challenges in gate level modeling for delay and SI at 65nm and below [J]. 2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 468 - 473
- [10] High accuracy 65nm OPC verification: Full process window model vs. critical failure ORC [J]. Optical Microlithography XVIII, Pts 1-3, 2005, 5754 : 1190 - 1201