Combining OPC and design for printability into 65nm logic designs

The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.