NAX: Neural Architecture and Memristive Xbar based Accelerator Co-design

被引:7
|
作者
Negi, Shubham [1 ]
Chakraborty, Indranil [1 ]
Ankit, Aayush [2 ]
Roy, Kaushik [1 ]
机构
[1] Purdue Univ, W Lafayette, IN 47907 USA
[2] Microsoft Corp, Mountain View, CA USA
基金
美国国家科学基金会;
关键词
D O I
10.1145/3489517.3530476
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Neural Architecture Search (NAS) has provided the ability to design efficient deep neural network (DNN) catered towards different hardwares like GPUs, CPUs etc. However, integrating NAS with Memristive Crossbar Array (MCA) based In-Memory Computing (IMC) accelerator remains an open problem. The hardware efficiency (energy, latency and area) as well as application accuracy (considering device and circuit non-idealities) of DNNs mapped to such hardware are co-dependent on network parameters such as kernel size, depth etc. and hardware architecture parameters such as crossbar size and the precision of analog-to-digital converters. Co-optimization of both network and hardware parameters presents a challenging search space comprising of different kernel sizes mapped to varying crossbar sizes. To that effect, we propose NAX - an efficient neural architecture search engine that co-designs neural network and IMC based hardware architecture. NAX explores the aforementioned search space to determine kernel and corresponding crossbar sizes for each DNN layer to achieve optimal tradeoffs between hardware efficiency and application accuracy. For CIFAR-10 and Tiny ImageNet, our models achieve 0.9% and 18.57% higher accuracy at 30% and -10.47% lower EDAP (energy-delay-area product), compared to baseline ResNet-20 and ResNet-18 models, respectively.
引用
收藏
页码:451 / 456
页数:6
相关论文
共 50 条
  • [1] CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework
    Tuli, Shikhar
    Li, Chia-Hao
    Sharma, Ritvik
    Jha, Niraj K.
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2023, 22 (03)
  • [2] SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning
    Liu, Siqin
    Karanth, Avinash
    2024 25TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED 2024, 2024,
  • [3] LACC:a hardware and software co-design accelerator for deep neural networks
    于涌
    Zhi Tian
    Zhou Shengyuan
    HighTechnologyLetters, 2021, 27 (01) : 62 - 67
  • [4] Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms
    Colangelo, Philip
    Segal, Oren
    Speicher, Alex
    Margala, Martin
    2019 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2019,
  • [5] LACC: a hardware and software co-design accelerator for deep neural networks
    Yu Y.
    Zhi T.
    Zhou S.
    High Technology Letters, 2021, 27 (01) : 62 - 67
  • [6] Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design
    Lee, Gwo Giun
    Wang, Ming-Jiun
    Chen, Bo-Han
    Chen, JiunFu
    Jao, Ping-Keng
    Hsiao, Ching Jui
    Wei, Ling-Fei
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2011, 63 (02): : 181 - 189
  • [7] Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design
    Gwo Giun Lee
    Ming-Jiun Wang
    Bo-Han Chen
    JiunFu Chen
    Ping-Keng Jao
    Ching Jui Hsiao
    Ling-Fei Wei
    Journal of Signal Processing Systems, 2011, 63 : 181 - 189
  • [8] Comprehensive Accelerator-Dataflow Co-design Optimization for Convolutional Neural Networks
    Vaidya, Miheer
    Sukumaran-Rajam, Aravind
    Rountev, Atanas
    Sadayappan, P.
    CGO '22: PROCEEDINGS OF THE 2022 IEEE/ACM INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION (CGO), 2022, : 325 - 335
  • [9] Deep Neural Network Model and FPGA Accelerator Co-Design: Opportunities and Challenges
    Hao, Cong
    Chen, Deming
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1413 - 1416
  • [10] Structuring the co-design of requirements and architecture
    Pohl, Klaus
    Sikora, Ernst
    REQUIREMENTS ENGINEERING: FOUNDATION FOR SOFTWARE QUALITY, 2007, 4542 : 48 - +