共 50 条
- [31] Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
- [32] Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
- [33] Challenges in Testing TSV-Based 3D Stacked ICs: Test Flows, Test Contents, and Test Access PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 544 - 547
- [34] TSV aware Standard Cell placement for 3D ICs 2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2015,
- [35] Electromagnetic susceptibility analysis method for 3D TSV ICs Yan, Zhaowen (yanzhaowen@buaa.edu.cn), 2017, Beijing University of Aeronautics and Astronautics (BUAA) (43): : 2406 - 2415
- [36] Fault Tolerant Techniques for TSV-based Interconnects in 3-D ICs 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 2577 - 2580
- [39] Distributed Multi TSV 3D Clock Distribution Network in TSV-based 3D IC 2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, : 87 - 90
- [40] 3D System Package Architecture as Alternative to 3D Stacking of ICs with TSV at System Level 2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,