Testable design of sequential circuits with improved fault efficiency

A new synthesis and design-for-testability (DFT) technique is proposed for improving farce efficiency in non-scan synchronous sequential circuits. Certain simple constraints are imposed on state encoding prior to synthesis, and then a DFT technique is employed that guarantees absence of all sequentially undetectable faults, such as invalid, equivalent and isomorph. If the netlist is available instead of state description. only the DFT technique is applied, by skipping the synthesis part. The proposed design guarantees significantly lower test generation time, higher fault coverage, and almost complete fault efficiency, when sequential test generation tools are used. Experiments on MCNC and ISCAS 89 benchmark circuits show encouraging results. Hardware overhead of the proposed method compares favorably with that of full-scan.