PATH-DELAY-FAULT TESTABLE NONSCAN SEQUENTIAL-CIRCUITS

被引：0

作者：

KE, W ^{[1
]}

MENON, PR ^{[1
]}

机构：

[1] UNIV MASSACHUSETTS, DEPT ELECT & COMP ENGN, AMHERST, MA 01003 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1995年 / 14卷 / 05期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/43.384419

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we show that any finite state machine can be implemented by a fully path-delay-fault testable nonscan sequential circuit. Synthesis methods are proposed, which use a one-hot encoding of states, a special circuit structure and at most one additional input. Combined with existing synthesis techniques for delay-fault testable combinational circuits, these methods can produce nonscan sequential circuits in which every path has a robust or validatable nonrobust test.

引用

页码：576 / 582

页数：7

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