Power Constraints Test Scheduling of 3D Stacked ICs

Core based 3D stacked ICs (3D SIGs) is an emerging area in today's semiconductor industry. Traditional testing approaches of 2D IC cannot he applied directly to 3D SICs. In this paper we have addressed a test scheduling approach that try to reduce the overall test application time (TAT) by optimizing the pre-bond and the post-bond test time while reckoning resource conflicts and satisfying power constraints. In addition we proposed distinct algorithms for wafer sort, partial overlapping in package test and rescheduling in package test Experimental results show that our proposed approach achieved better reduced TAT compared to [1].