A 60 GHz power amplifier in 90nm CMOS technology

被引：14
|
作者：
Heydari, Babak [1 ]
Bohsali, Mounir [1 ]
Adabi, Ehsan [1 ]
Niknejad, Ali M. [1 ]
机构：
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源：
PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2007年
关键词：
D O I：
10.1109/CICC.2007.4405843
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A two-stage 60 GHz 90nm CMOS PA has been designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output power. The measured P-1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main PA for short range wireless communication. The output power can be boosted with on-chip or spatial power combining.
引用
收藏
页码：769 / 772
页数：4
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