Optimization of Stacked Nanoplate FET for 3-nm Node

被引：11
|
作者：
Kim, Hyunsuk [1 ,2 ]
Son, Dokyun [1 ,2 ]
Myeong, Ilho [1 ,2 ]
Park, Jaeyeol [1 ,2 ]
Kang, Myounggon [3 ]
Jeon, Jongwook [4 ]
Shin, Hyungcheol [1 ,2 ]
机构：
[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea
[2] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea
[3] Korea Natl Univ Transportat, Dept Elect Engn, Chungju Si 151742, South Korea
[4] Konkuk Univ, Dept Elect Engn, Seoul 05029, South Korea
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2020年 / 67卷 / 04期
关键词：
MOS devices; Field effect transistors; Degradation; Delays; Performance evaluation; Capacitance; Calibration; FinFET; nanoplate FET; self-heating effects (SHEs);
D O I：
10.1109/TED.2020.2976041
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.
引用
收藏
页码：1537 / 1541
页数：5
相关论文
共 50 条
  • [41] Geometrical Variability Impact on the Performance of Sub-3 nm Gate-All-Around Stacked Nanosheet FET
    Yadav, Nisha
    Jadav, Sunil
    Saini, Gaurav
    SILICON, 2022, 14 (16) : 10681 - 10693
  • [42] Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications
    Yun, Hyeok
    Yoon, Jun-Sik
    Jeong, Jinsu
    Lee, Seunghwan
    Choi, Hyun-Chul
    Baek, Rock-Hyun
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2020, 8 : 1272 - 1280
  • [43] Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications
    Yun, Hyeok
    Yoon, Jun-Sik
    Jeong, Jinsu
    Lee, Seunghwan
    Choi, Hyun-Chul
    Baek, Rock-Hyun
    2020 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2020), 2020,
  • [44] ELECTRON-DIFFRACTION FROM AREAS LESS THAN 3-NM IN DIAMETER
    GEISS, RH
    APPLIED PHYSICS LETTERS, 1975, 27 (04) : 174 - 176
  • [45] Fabrication of 3-nm Platinum Wires Using a Tobacco Mosaic Virus Template
    Kobayashi, Mime
    Onodera, Katsuya
    Watanabe, Yuichiro
    Yamashita, Ichiro
    CHEMISTRY LETTERS, 2010, 39 (06) : 616 - 618
  • [46] Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology
    Gao, Zhan
    Hu, Min-Chun
    Baert, Rogier
    Chehab, Bilal
    Swenton, Joe
    Malagi, Santosh
    Huisken, Jos
    Goossens, Kees
    Marinissen, Erik Jan
    IEEE DESIGN & TEST, 2024, 41 (02) : 56 - 64
  • [47] 1.2 nm HfSiON/SiON stacked gate insulators for 65-nm-node MISFETs
    Saitoh, M
    Terai, M
    Ikarashi, N
    Watanabe, H
    Fujieda, S
    Iwamoto, T
    Ogura, T
    Morioka, A
    Watanabe, K
    Tatsumi, T
    Watanabe, H
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (4B): : 2330 - 2335
  • [48] 1.2 nm HfSiON/SiON stacked gate insulators for 65-nm-Node MISFETs
    Saitoh, Motofumi
    Terai, Masayuki
    Ikarashi, Nobuyuki
    Watanabe, Heiji
    Fujieda, Shinji
    Iwamoto, Toshiyuki
    Ogura, Takashi
    Morioka, Ayuka
    Watanabe, Koji
    Tatsumi, Toru
    Watanabe, Hirohito
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2005, 44 (4 B): : 2330 - 2335
  • [49] Plasma-induced charging damage in ultrathin (3-nm) gate oxides
    Chen, CC
    Lin, HC
    Chang, CY
    Liang, MS
    Chien, CH
    Hsien, SK
    Huang, TY
    Chao, TS
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (07) : 1355 - 1360
  • [50] Processable 3-nm thick graphene platelets of high electrical conductivity and their epoxy composites
    Meng, Qingshi
    Jin, Jian
    Wang, Ruoyu
    Kuan, Hsu-Chiang
    Ma, Jun
    Kawashima, Nobuyuki
    Michelmore, Andrew
    Zhu, Shenmin
    Wang, Chun H.
    NANOTECHNOLOGY, 2014, 25 (12)
12345