Optimization of Stacked Nanoplate FET for 3-nm Node

被引：11

作者：

Kim, Hyunsuk ^{[1
,2
]}

Son, Dokyun ^{[1
,2
]}

Myeong, Ilho ^{[1
,2
]}

Park, Jaeyeol ^{[1
,2
]}

Kang, Myounggon ^{[3
]}

Jeon, Jongwook ^{[4
]}

Shin, Hyungcheol ^{[1
,2
]}

机构：

[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea

[2] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea

[3] Korea Natl Univ Transportat, Dept Elect Engn, Chungju Si 151742, South Korea

[4] Konkuk Univ, Dept Elect Engn, Seoul 05029, South Korea

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2020年 / 67卷 / 04期

关键词：

MOS devices; Field effect transistors; Degradation; Delays; Performance evaluation; Capacitance; Calibration; FinFET; nanoplate FET; self-heating effects (SHEs);

D O I：

10.1109/TED.2020.2976041

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.

引用

页码：1537 / 1541

页数：5

共 50 条

[31] A TUNABLE SPECTROMETERDIODE WITH A SPECTRAL RESOLUTION OF 3-NM IN THE 660-900-NM RANGE
ALBERTSHOFER, W
SENSORS AND ACTUATORS A-PHYSICAL, 1991, 26 (1-3) : 443 - 447
[32] Asymmetric disturbance and permeabilization of bilayer membranes by 3-nm carbon dots
Li, Wenwen
Ma, Yurong
Ou, Luping
Xu, Cheng
Wei, Yushuang
Yang, Kai
Yuan, Bing
JOURNAL OF HAZARDOUS MATERIALS, 2024, 465
[33] Vertical Slit FET at 7-nm Node and Beyond
Yang, Ping-Lin
Hook, Terence B.
Oldiges, Philip J.
Doris, Bruce B.
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (08) : 3327 - 3334
[34] Optimization of junctionless stacked nanosheet FET - RF stability perspective
Balasubbareddy, M.
Sivasankaran, K.
MICROELECTRONICS JOURNAL, 2024, 145
[35] Geometrical Variability Impact on the Performance of Sub - 3 nm Gate-All-Around Stacked Nanosheet FET
Nisha Yadav
Sunil Jadav
Gaurav Saini
Silicon, 2022, 14 : 10681 - 10693
[36] POSSIBLE MONOCHROMATIC ION-BEAM LAMPS AT 4-NM AND 3-NM WAVELENGTHS
PILKUHN, H
OPTICS COMMUNICATIONS, 1991, 82 (1-2) : 34 - 36
[37] Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets
Hook, Terence B.
JOULE, 2018, 2 (01) : 1 - 4
[38] Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET
Narasimham, B.
Montoya, A. R.
Paone, C.
Riehle, T.
Smith, M.
Tsau, L.
Ball, D.
Bhuva, B.
2024 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS 2024, 2024,
[39] Optimization of vertically stacked nanosheet FET immune to self-heating
Balasubbareddy, M.
Sivasankaran, K.
Atamuratov, Atabek E.
Khalilloev, Mahkam M.
MICRO AND NANOSTRUCTURES, 2023, 182
[40] Via Size Optimization for Optimum Circuit Performance at 3 nm node
Mittal, Sushant
Pal, Ashish
Saremi, Mehdi
Bazizi, El Mehdi
Alexander, Blessy
Ayyagari, Buvna
2020 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2020), 2020, : 327 - 330

← 1 2 3 4 5 →