On the Design and Analysis of Quaternary Serial and Parallel Adders

被引：1

作者：

Das, Anindya ^{[1
]}

Jahangir, Ifat ^{[1
]}

Hasan, Masud ^{[2
]}

Hossain, Shahera ^{[3
]}

机构：

[1] Bangladesh Univ Engn & Technol, Dept Elect & Elect Engn, Dhaka 1000, Bangladesh

[2] Bangladesh Univ Engn & Technol, Dept Comp Sci & Engn, Dhaka 1000, Bangladesh

[3] Kyushu Inst Technol, Dept Elect & Comp Engn, Kitakyushu, Fukuoka, Japan

来源：

TENCON 2010: 2010 IEEE REGION 10 CONFERENCE | 2010年

关键词：

Logarithmic stage adder; Quaternary fast adder; Quaternary full adder; Ripple carry adder;

D O I：

10.1109/TENCON.2010.5686045

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log(2)( n) time delay for n qudits. At last, we compare the gate delays of full adder and logarithmic stage parallel adder with the help of mathematical expressions.

引用

页码：1691 / 1695

页数：5

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