On the Design and Analysis of Quaternary Serial and Parallel Adders

被引：1
|
作者：
Das, Anindya [1 ]
Jahangir, Ifat [1 ]
Hasan, Masud [2 ]
Hossain, Shahera [3 ]
机构：
[1] Bangladesh Univ Engn & Technol, Dept Elect & Elect Engn, Dhaka 1000, Bangladesh
[2] Bangladesh Univ Engn & Technol, Dept Comp Sci & Engn, Dhaka 1000, Bangladesh
[3] Kyushu Inst Technol, Dept Elect & Comp Engn, Kitakyushu, Fukuoka, Japan
来源：
TENCON 2010: 2010 IEEE REGION 10 CONFERENCE | 2010年
关键词：
Logarithmic stage adder; Quaternary fast adder; Quaternary full adder; Ripple carry adder;
D O I：
10.1109/TENCON.2010.5686045
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Optimization techniques for decreasing the time and chip area of adder circuits have been thoroughly studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We provide the design of a logarithmic stage parallel adder which can compute the carries within log(2)( n) time delay for n qudits. At last, we compare the gate delays of full adder and logarithmic stage parallel adder with the help of mathematical expressions.
引用
收藏
页码：1691 / 1695
页数：5
相关论文
共 50 条
  • [1] Design of Adders with Quaternary logic
    Hajare, Shweta
    Dakhole, Pravin
    2015 INTERNATIONAL CONFERENCE ON INDUSTRIAL INSTRUMENTATION AND CONTROL (ICIC), 2015, : 599 - 601
  • [2] Design of high performance Quaternary adders
    Patel, Vasundara K. S.
    Gurumurthy, K. S.
    2011 41ST IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL), 2011, : 22 - 26
  • [3] Design and analysis of carbon nanotube FET based quaternary full adders
    Mohammad Hossein Moaiyeri
    Shima Sedighiani
    Fazel Sharifi
    Keivan Navi
    Frontiers of Information Technology & Electronic Engineering, 2016, 17 : 1056 - 1066
  • [4] Design and analysis of carbon nanotube FET based quaternary full adders
    Moaiyeri, Mohammad Hossein
    Sedighiani, Shima
    Sharifi, Fazel
    Navi, Keivan
    FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, 2016, 17 (10) : 1056 - 1066
  • [5] An Analysis of Parallel Prefix Adders Regarding the Design of Low-Power Data Oriented Adders
    Brzozowski, Ireneusz
    2018 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS (ICSES 2018), 2018, : 7 - 12
  • [6] DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS
    Govindaraj, Prabakaran
    Nallasamy, Shanmugasundaram
    Mylsamy, Mohankumar
    Krishnamoorthy, Sathiyapriya
    SURANAREE JOURNAL OF SCIENCE AND TECHNOLOGY, 2024, 31 (01): : (1 - 8)
  • [7] Design alternatives for parallel saturating multioperand adders
    Balzola, PI
    Schulte, MJ
    Ruan, J
    Glossner, J
    Hokenek, E
    2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 2001, : 172 - 177
  • [8] FPGA Implementation and Performance Analysis of Parallel Prefix Structures for Modular Adders Design
    Gupta, Tukur
    Verma, Gaurav
    Akhter, Shamim
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2025, 44 (02) : 992 - 1016
  • [9] Design and analysis of a hybrid serial-parallel manipulator
    Romdhane, L
    MECHANISM AND MACHINE THEORY, 1999, 34 (07) : 1037 - 1055
  • [10] PIPELINED BINARY PARALLEL COUNTERS EMPLOYING LATCHED QUATERNARY LOGIC FULL ADDERS
    CURRENT, KW
    IEEE TRANSACTIONS ON COMPUTERS, 1980, 29 (05) : 400 - 403
12345