A development and simulation environment for a floating point operations FPGA based accelerator

被引：2

作者：

Bera, M ^{[1
]}

Danese, G ^{[1
]}

De Lotto, I ^{[1
]}

Leporati, F ^{[1
]}

Spelgatti, A ^{[1
]}

机构：

[1] Univ Pavia, Dipartimento Informat & Sistemist, INFM, Sez Pavia, I-27100 Pavia, Italy

来源：

EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/DSD.2003.1231922

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Exploiting hardware devoted to a specific application requires a proper programming support, like libraries allowing a simple interface with the device. As a complementary design, a dedicated device language might be developed to make its programming easier. In previous works [1][2] we presented the architecture of a floating point operations accelerator based on Field Programmable Gate Array (FPGA) technology. In this paper we describe the development environment which allows to write, translate and simulate instruction sequences written in a language specifically conceived and designed for that device.

引用

页码：173 / 179

页数：7

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