Floating-point matrix product on FPGA

The nature of some scientific computing applications involves performing complex tasks repeatedly on floating-point data, often under real-time requirements. Therefore, high performance systems are required by the developers for fast computations. Many researchers have begun to recognize the potential of reconfigurable hardware such as field-programable gate arrays in implementing floating-point arithmetic. In this paper a floating-point adder and multiplier are presented. The proposed cores are used as basic components for the implementation of a parallel floating-point matrix multiplier designed for 3D affine transformations. The cores have been implemented on recent FPGA devices. The performance in terms of area/speed of the proposed architectures has been assessed and has shown that they require less area and can be run with a higher frequency when compared with existing systems.