Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs

In this paper, an analytical model for parasitic gate capacitances in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is developed for the first time. A practical 3-D architecture of SNWTs with surrounding-gate cylindrical channel and source/drain extension regions is taken into account in the parasitic gate capacitance modeling. The parasitic gate capacitances of the SNWT are divided into four parts: 1) outer fringe capacitance C-of; 2) inner fringe capacitance C-if; 3) overlap capacitance C-ov; and 4) sidewall capacitance C-side. The 3-D capacitance system is calculated by useful methods such as the equivalent transformation and inversion of Schwarz-Christoffel mapping. The obtained model agrees well with the results of 3-D electrostatic numerical simulations. The results show that the proportion of parasitic gate capacitances in the total capacitance is increased in this gate-all-around architecture due to the ultrasmall dimension of the SNWT channel; thus, the proportion of the intrinsic capacitance is reduced. Among the capacitances, C-of is found to be the largest contributor to the total parasitic gate capacitance in FO1 delay calculation, and C-side manifests itself as a nonnegligible parasitic capacitance. The developed capacitance model can be easily incorporated into a compact core model of SNWTs for further device/circuit design optimizations with various device parameters.