Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET

Lateral nanosheet field-effect-transistor (FET) is now targeting for 3nm CMOS technology node [1], [2]. It is important to see quantization effect at such confined geometry. In this work, we study the geometrical confinement effects in silicon nanosheet. We developed a unified phenomenological model for insulator capacitance (C-ins) in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET to solve the gate charge density accurately. It is observed that multi-subband conduction causes humps in higher order derivatives of charge vs gate voltage characteristics which may affect the performance of analog and RF circuits.