An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits

被引：22

作者：

Huang, Yi-Chieh ^{[1
,2
]}

Wang, Ping-Ying ^{[1
,2
]}

Liu, Shen-Iuan ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2012年 / 59卷 / 03期

关键词：

All-digital; clock and data recovery; jitter tolerance; DATA-RECOVERY CIRCUIT; BANG-BANG CLOCK;

D O I：

10.1109/TCSII.2012.2184378

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13% in the frequency range of 178 kHz similar to 11.3 MHz. The measured peak-to-peak data and clock jitters are 15.56 and 13.3 ps. The power of the CDR circuit is 44.4 mW at a supply voltage of 1.2 V.

引用

页码：148 / 152

页数：5

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