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- [31] Scan-based BIST diagnosis using an embedded processor 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 209 - 216
- [32] A ROMless LFSR reseeding scheme for scan-based BIST PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02), 2002, : 206 - 211
- [33] Switching activity reduction for scan-based BIST using weighted scan input data IEICE ELECTRONICS EXPRESS, 2012, 9 (10): : 874 - 880
- [34] Low power BIST based on scan partitioning DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, 2005, : 33 - 41
- [35] A gated clock scheme for low power scan-based BIST SEVENTH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, PROCEEDINGS, 2001, : 87 - 89
- [36] A scan matrix design for low power scan-based test 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 224 - 229
- [37] Improved fault diagnosis in scan-based BIST via superposition 37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, : 55 - 58
- [38] Pseudo-functional scan-based BIST for delay fault 23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 229 - 234