A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects

被引：0
|
作者：
Fu, Bo [1 ]
Ampadu, Paul [1 ]
机构：
[1] Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USA
来源：
NANO-NET | 2009年 / 3卷
关键词：
Adaptive error control; on-chip interconnects; hybrid ARQ; interleaving; NETWORKS;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a dual-mode hybrid ARQ scheme for energy efficient on-chip communication, where the type of coding scheme can be dynamically selected based on different noise environments and reliability requirements. In order to reduce codec area overhead, a hardware sharing design method is implemented, resulting in only a minor increase in area costs compared to a single-mode system. For a given reliability requirement, the proposed error control scheme yields up to 35% energy improvement compared to previous solutions and up to 18% energy improvement compared to worst-case noise design method.
引用
收藏
页码：74 / 79
页数：6
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