VLSI-oriented input and output buffered switch architecture for high-speed ATM backbone nodes

被引：0

作者：

Kamatani, Y ^{[1
]}

Ohba, Y ^{[1
]}

Shimojo, Y ^{[1
]}

Ise, K ^{[1
]}

Motoyama, M ^{[1
]}

Saito, T ^{[1
]}

机构：

[1] TOSHIBA CO LTD, SEMICOND DEVICE ENGN LAB, KAWASAKI, KANAGAWA 210, JAPAN

来源：

IEICE TRANSACTIONS ON COMMUNICATIONS | 1996年 / E79B卷 / 05期

关键词：

ATM; switch; node; high-speed; backbone; flow control; input buffer; output buffer; shaved buffer; multicast; QoS; LSI;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Asynchronous Transfer Mode (ATM) is a promised bearer transmission service for high speed multimedia LAN. Recently, high speed multimedia ATM LAN products have been available. Therefore, in order to interconnect them, the multimedia backbone LAN, which has the expandable high throughput over 10G bps, supporting multicast, multi-QoS, and many interfaces including 622 Mbps, will be widely required. In this paper, the VLSI oriented input and output buffered switch architecture is proposed as the hardware architecture for multimedia backbone switch node. This paper describes that the chip set consisting of four VLSIs, that is, the switch element, the switch access, the distributor/arbiter, and the multiplexer/demultiplexer, can realize the backbone switch core, and the main specifications required to each VLSI are derived.

引用

页码：647 / 657

页数：11

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