Ultra low power four-quadrant multiplier/two-quadrant divider circuit using FGMOS

被引：2
|
作者：
Rodriguez-Villegas, E. [1 ]
Alam, Loannis [1 ]
机构：
[1] Univ London Imperial Coll Sci Technol & Med, Dept Elect & Elect Engn, Exhibit Rd, London SW7 2BT, England
来源：
IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II | 2006年
关键词：
D O I：
10.1109/MWSCAS.2006.382209
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a novel ultra low power wide-range four-quadrant multiplier/two-quadrant divider circuit. The proposed circuit is implemented using Floating Gate MOS (FGMOS) devices operating in weak inversion. The wide range is achieved by means of a predistortion technique based on having different input capacitances in the FGMOS transistors. The circuit compares favourably to other ultra low power multiplier/divider circuits. The multiplier/divider can operate under a 0.9V supply voltage with a power consumption of 87nW in a 0.35 mu m AMS technology.
引用
收藏
页码：64 / +
页数：2
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