A novel four-quadrant/one-quadrant multiplier circuit

A novel current-mode analog multiplier is presented, in which a novel squarer cell and a low-power current mirror have been employed to obtain a low-power consumption circuit. The proposed architectures for the squarer cell and the multiplier circuit allow the operation both in one-quadrant and four-quadrants. The multiplier has been designed in TSMC 180nm CMOS technology and, to validate the circuit performance, it has been simulated using CADENCE software. In the four-quadrant configuration, post-layout simulation results demonstrate a linearity error of 0.63%, a THD of 0.41% in 1 MHz, a 3-dB bandwidth of 173 MHz with 1.4 V supply voltage, and maximum power consumption of approximately 340 mu W. Using the one-quadrant configuration, the maximum power consumption was 55 mu W with 1.1 V supply voltage. The quiescent power was 75 mu W for the four-quadrants configuration and approximately 0 mu W for the one-quadrant configuration.