CMOS wme-range four-quadrant analog multiplier circuit

被引:0
|
作者
Prommee, P [1 ]
Somdunyakanok, M [1 ]
Poorahong, K [1 ]
Phinat, P [1 ]
Dejhan, K [1 ]
机构
[1] King Mongkuts Inst Technol, Fac Engn, Bangkok 10520, Thailand
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
A wide-range CMOS analog multiplier based-upon a quarter square algebraic identity technique is proposed. The transistors are operated in the both of saturation and ohmic regions. It consists of shunt-feedback buffer and active attenuator circuits that obtained to the voltage regulation circuits. This paper uses 16 transistors and 4 current sources with a +/- 1.5V power supply. The wide input dynamic range voltage can be achieved reaching the power supply. The bandwidth is rather than 141 MHz and total harmonic distortion is smaller than 0.7%. The results are carried out by PSpice simulation program.
引用
收藏
页码:197 / 200
页数:4
相关论文
共 50 条
  • [1] Analog CMOS four-quadrant multiplier and divider
    Vlassis, S
    Siskos, S
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: SYSTEMS, POWER ELECTRONICS, AND NEURAL NETWORKS, 1999, : 383 - 386
  • [2] CMOS Fully Differential CMOS Four-Quadrant Analog Multiplier
    Mahmoud, Soliman A.
    [J]. 2008 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2008, : 27 - 30
  • [3] CMOS Design and Analysis of Four-Quadrant Analog Multiplier Circuit for LF Applications
    Gond, Abhishek Kumar
    Pandit, Soumya
    [J]. PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION, DEVICES AND COMPUTING, 2020, 602 : 279 - 289
  • [4] Four-quadrant analog multiplier based on CMOS inverters
    Machowski, W.
    Kuta, S.
    Jasielski, J.
    [J]. PROCEEDINGS OF THE INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, : 290 - +
  • [5] Four-quadrant analog multiplier based on CMOS inverters
    Witold Machowski
    Stanisław Kuta
    Jacek Jasielski
    [J]. Analog Integrated Circuits and Signal Processing, 2008, 55 : 249 - 259
  • [6] Four-quadrant analog multiplier based on CMOS inverters
    Machowski, Witold
    Kuta, Stanistaw
    Jasielski, Jacek
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2008, 55 (03) : 249 - 259
  • [7] A 1.2 V CMOS four-quadrant analog multiplier
    Hsiao, SY
    Wu, CY
    [J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 241 - 244
  • [8] A wide dynamic range four-quadrant CMOS analog multiplier using active feedback
    Huang, Zhangcai
    Inoue, Yasuaki
    Yu, Hong
    Zhang, Quan
    [J]. 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 708 - +
  • [9] A 1.2-V CMOS four-quadrant analog multiplier
    Blalock, BJ
    Jackson, SA
    [J]. 1999 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, SSMSD 99, 1999, : 1 - 4
  • [10] A New CMOS Four-quadrant Analog Multiplier with Differential Output
    Saatlo, Ali Naderi
    Amiri, Abolfazl
    Asadpour, Loghman
    [J]. 2015 INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD), 2015,