Design of a 3T Current Reference for Low-Voltage, Low-Power Operation

This paper focuses on the design of a 3-transistor (3T) current reference, which allows sub-1-V nanopower operation. The impact of the basic electrical and geometrical parameters of the three transistors on circuit performance is discussed by means of simulations in a commercial 0.18 mu m CMOS technology. We also report experimental results on a test chip, which are consistent with the simulation predictions. When compared to state-of-the-art nanopower competitors, the fabricated circuit proves to be a competitive candidate thanks to the very low minimum operating voltage (0.45 V) and small area occupation (only 750 mu m(2)), while exhibiting competitive performance in terms of temperature coefficient (578 ppm/degrees C) and power consumption (213 nW).