Design of a 3T Current Reference for Low-Voltage, Low-Power Operation

被引：0

作者：

De Rose, Raffaele ^{[1
]}

Crupi, Felice ^{[1
]}

Paliy, Maksym ^{[2
]}

Lanuzza, Marco ^{[1
]}

Iannaccone, Giuseppe ^{[2
]}

机构：

[1] Univ Calabria, Dept Comp Engn Modeling Elect & Syst Engn, I-87036 Arcavacata Di Rende, Italy

[2] Univ Pisa, Dept Informat Engn, I-56122 Pisa, Italy

来源：

2018 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2018) | 2018年

关键词：

Current reference; CMOS analog design; low power; low voltage; CURRENT REFERENCE CIRCUIT;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper focuses on the design of a 3-transistor (3T) current reference, which allows sub-1-V nanopower operation. The impact of the basic electrical and geometrical parameters of the three transistors on circuit performance is discussed by means of simulations in a commercial 0.18 mu m CMOS technology. We also report experimental results on a test chip, which are consistent with the simulation predictions. When compared to state-of-the-art nanopower competitors, the fabricated circuit proves to be a competitive candidate thanks to the very low minimum operating voltage (0.45 V) and small area occupation (only 750 mu m(2)), while exhibiting competitive performance in terms of temperature coefficient (578 ppm/degrees C) and power consumption (213 nW).

引用

页码：13 / 16

页数：4

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