High Speed VLSI Architecture Design Using FFT for 5G Communications

被引：0

作者：

Devi, P. Lakshmi ^{[1
]}

Malipatil, Somashekhar ^{[2
]}

Surekha, P. S. ^{[2
]}

机构：

[1] St Peeters Engn Coll A, Dept Elect & Commun Engn, Hyderabad, Telangana, India

[2] Malla Reddy Engn Coll & Management Sci, Dept Elect & Commun Engn, Medchal, Telangana, India

来源：

INVENTIVE COMPUTATION AND INFORMATION TECHNOLOGIES, ICICIT 2021 | 2022年 / 336卷

关键词：

Coordinate rotation digital computer (CORDIC); FFT; DFT; Xilinx ISE 14.7; Verilog; 5G; VLSI; PROCESSOR;

D O I：

10.1007/978-981-16-6723-7_22

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high speed FFT processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point DFTs for 5G, WLAN. The processor is designed for high speed applications and source code is written in Verilog. Synthesis and simulation is done in Xilinx ISE 14.7. The power dissipation is minimized (20.3 mW) and delay is 9.539 ns and further extension is done using CORDIC processor delay is 7.55 ns. In this paper, high speed VLSI Architecture designed using FFT for 5G Communications. The proposed results are compared with the existed work.

引用

页码：297 / 304

页数：8

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