A 4.9-GHz low power, low jitter, LC phase locked loop

被引：4

作者：

Liu, T. ^{[1
]}

机构：

[1] So Methodist Univ, Dallas, TX 75275 USA

来源：

JOURNAL OF INSTRUMENTATION | 2010年 / 5卷

关键词：

VLSI circuits; Analogue electronic circuits; Front-end electronics for detector readout;

D O I：

10.1088/1748-0221/5/12/C12045

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-mu m m Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has been investigated and traced to the first stage of the divider chain. The power consumption at the central frequency is 111 mW.

引用

页数：9

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