A low power sample-and-hold amplifier

被引：0

作者：

Tani, H ^{[1
]}

Fujimoto, Y ^{[1
]}

Maruyama, M ^{[1
]}

Akada, H ^{[1
]}

Ogawa, H ^{[1
]}

Miyamoto, M ^{[1
]}

机构：

[1] Sharp Co Ltd, Adv Technol Res Labs, Tenri, Nara, Japan

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257176

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel power reduction technique is proposed for a sample-and-hold amplifier (SHA) with two stage operational amplifier. This technique improves the bandwidth and the slew rate of the SHA, therefore the power consumption of the SHA can be reduced. A variable gain amplifier (VGA) used in an analog-digital interface system for mega-pixel CCD image sensors is implemented. Fabricated in 0.25-mum CMOS process with MIM capacitors, the VGA occupies 0.49 x 0.49 mm(2) and dissipates 18.7 mW at 18 MHz with a supply voltage of 3.1 V.

引用

页码：477 / 480

页数：4

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