Hardware Co-simulation of Reconfigurable FIR Filters on FPGA

Field programmable gate array (FPGA) provides an attractive platform for realization of different logical functions and hardware components frequently used in digital signal processing (DSP) applications. These platforms present new challenges for logic and hardware designers, particularly for the module that involves the mapping of desired functionality onto the underlying prefabricated reconfigurable hardware resources. A fundamental aspect of the DSP is filtering. Digital filters having finite duration of impulse responses are referred to as finite impulse response (FIR) filters. This paper mainly emphasizes on the design and implementation of FIR filters of different forms in FPGA. The proposed design algorithm of FIR is modeled in VHDL followed by verification and synthesis using the XST tool. The performance of FIR is analyzed using the timing diagrams, HDL synthesis report, and device utilization summary. This work also incorporates hardware co-simulation of the system with real filter analysis.