FPGA Hardware-in-loop Co-simulation for THIPWM Controlled Multilevel Inverter

被引：0

作者：

Pandey, Ravikant ^{[1
]}

Tripathi, Ravi Nath ^{[2
]}

Hanamoto, Tsuyoshi ^{[1
]}

机构：

[1] Kyushu Inst Technol, Grad Sch Life Sci & Syst Engn, Kitakyushu, Fukuoka 8070815, Japan

[2] Kyushu Inst Technol, Next Generat Power Elect Res Ctr, Kitakyushu, Fukuoka 8070815, Japan

来源：

2017 3RD IEEE CONFERENCE ON ENERGY CONVERSION (CENCON) | 2017年

基金：

日本学术振兴会;

关键词：

THIPWM; FPGA; Hardware-in-loop; Co-siumulation;

D O I：

暂无

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

In this paper,FPGA(Field Programmable Gate Array) hardware-in-loop co-simulation (Hardware co-simulation)is proposed for controller prototyping of Cascaded H-bridge multilevel inverter(CHBMLI).Third harmonics injected pulse width modulation(THIPWM) technique is used for controller prototyping.Mathematical analysis of THIPWM control is investigated for improved dc bus voltage utilization and extension of linearity range. Control model of THIPWM for five and seven level inverter incorporating Phase shifted and level shifted carrier signals are generated using Xilinx system generator(XSG) platform in Matlab/simulink.Real time Hardware co-simulation is performed by modelling CHBMLI system in Matlab/simulink and hardware co-simulation is performed using Zedboard Zynq development and evaluation FPGA kit.

引用

页码：32 / 37

页数：6

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