Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs (vol 59, pg 3, 2012)

被引：3
|
作者：
Zou, Jibin
Xu, Qiumin
Luo, Jieying
Wang, Runsheng
Huang, Ru
Wang, Yangyuan
机构：
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2012年 / 59卷 / 03期
关键词：
D O I：
10.1109/TED.2011.2178417
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：867 / 867
页数：1
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