A 500-MS/s 8-b Low Power High Speed Asynchronous SAR ADC in 40-nm CMOS

被引：1
|
作者：
Ding, Bowen [1 ]
Miao, Peng [1 ]
Li, Fei [1 ]
机构：
[1] Sch Southeast, Nanjing, Peoples R China
来源：
2019 5TH INTERNATIONAL CONFERENCE ON FRONTIERS OF SIGNAL PROCESSING (ICFSP 2019) | 2019年
关键词：
Analog-to-digital converter; asynchronous logic; successive approximation algorithm; capacitor array; low power;
D O I：
10.1109/icfsp48124.2019.8938045
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents a 500-MS/s 8-b single-channel asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that achieves low input frequency SNDR/SFDR of 45.89/58.9 dB, while the SNDR/SFDR near Nyquist is 44.75/58.8 dB with excellent power efficiency. The ADC adopts background digital detection with analog calibration techniques to correct offset mismatch. The high linearity is guaranteed by a kind of fast input bootstrapped circuits as the input switches. Furthermore, the proposed double-tail dynamic comparator and Set-and-Down structure capacitive digital-to-analog converter (CDAC) save the overall energy. The total power consumption is 0.61mW under a 1.1-V supply.
引用
收藏
页码：136 / 140
页数：5
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