Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes

被引：1

作者：

Wu, Yang Bo ^{[1
]}

Hu, Jian Ping ^{[1
]}

Li, Hong ^{[1
]}

机构：

[1] Ningbo Univ, Fac Informat Sci & Technol, Ningbo 315211, Zhejiang, Peoples R China

来源：

PROGRESS IN MEASUREMENT AND TESTING, PTS 1 AND 2 | 2010年 / 108-111卷

关键词：

leakage power; power estimation; adiabatic logic; SPICE simulation; LOGIC;

D O I：

10.4028/www.scientific.net/AMR.108-111.625

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

引用

页码：625 / 630

页数：6

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