A precise model for leakage power estimation in VLSI circuits

被引：2

作者：

Derakhshandeh, J ^{[1
]}

Masoumi, N ^{[1
]}

Kasiri, B ^{[1
]}

Farazmand, Y ^{[1
]}

Akbarzadeh ^{[1
]}

Aghnoot, S ^{[1
]}

机构：

[1] Univ Tehran, VLSI Res Grp, Tehran, Iran

来源：

FIFTH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/IWSOC.2005.23

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Leakage current is becoming very important factor in determining the feasibility of designs, today. Due to exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by a linear model. In the first model the inputs are the number of all gates that used in circuit. And in the second model inputs are the number of gates and in the third model inputs are the number of input states of gates. The model is validated for a large benchmark circuits and the leakage power predicted by our model is within 5% of the actual leakage power predicted by a popular tool used in the industry.

引用

页码：337 / 340

页数：4

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