Area-efficient video transform for HEVC applications

被引：5
|
作者：
Chen, Yuan-Ho [1 ]
Liu, Chieh-Yang [2 ]
机构：
[1] Chang Gung Univ, Dept Elect Engn, Tao Yuan 333, Taiwan
[2] Chung Yuan Christian Univ, Dept Informat & Comp Engn, Zhongli City 320, Taiwan
来源：
ELECTRONICS LETTERS | 2015年 / 51卷 / 14期
关键词：
video coding; inverse transforms; area-efficiency video transform; HEVC; high-efficiency video coding; inverse transform; 32-point transform unit; single one-dimensional transform core;
D O I：
10.1049/el.2015.1085
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores.
引用
收藏
页码：1065 / 1066
页数：2
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