Power and Area Efficient VLSI Architectures for Communication Signal Processing

被引：0

作者：

Markovic, Dejan ^{[1
]}

Nikolic, Borivoje ^{[1
]}

Brodersen, Robert W. ^{[1
]}

机构：

[1] Univ Calif Berkeley, Berkeley Wireless Res Ctr, Berkeley, CA 94704 USA

来源：

2006 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-12 | 2006年

关键词：

Circuit synthesis; design methodology; architecture; adaptive signal processing; matrix decomposition; MIMO systems;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A methodology for VLSI realization of signal processing algorithms for wireless communications is presented that optimizes architecture for reduced power and area. When power is limited, optimal architecture represents a point on the best power-area tradeoff curve that is obtained by balancing the algorithm throughput with the power-performance tradeoff of the underlying building blocks. Architectural optimization is done in the graphical Matlab/Simulink environment, which is also used for algorithm verification. Hardware description language produced by Simulink enables algorithm emulation on the FPGA and also serves as design entry for the chip realization. This is illustrated on complex multi-dimensional algorithms such as wideband MIMO channel decoupling through singular value decomposition (SVD) using 16 sub-carriers.

引用

页码：3223 / 3228

页数：6

共 50 条

[1] Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
Bose, Sudipta
De, Arijit
Chakrabarti, Indrajit
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68 (11) : 3451 - 3455
[2] Area Efficient VLSI Architectures for Weak Signal Detection in Additive Generalized Cauchy Noise
Vadali, Siva Ram Krishna
Mula, Subralunanyam
Ray, Priyadip
Chakrabarti, Saswat
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (06) : 1962 - 1975
[3] Efficient VLSI architectures for baseband signal processing in wireless base-station receivers
Rajagopal, S
Bhashyam, S
Cavallaro, JR
Aazhang, B
IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, PROCEEDINGS, 2000, : 173 - 184
[4] ARCHITECTURES FOR VLSI CIRCUITS IN DIGITAL SIGNAL-PROCESSING
LACROIX, A
COMPUTER NETWORKS AND ISDN SYSTEMS, 1982, 6 (03): : 225 - 227
[5] AREA-EFFICIENT VLSI ARCHITECTURES FOR HUFFMAN CODING
PARK, H
PRASANNA, VK
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1993, 40 (09): : 568 - 575
[6] CORDIC- Based VLSI architectures for digital signal processing
Hu, Yu Hen
IEEE SIGNAL PROCESSING MAGAZINE, 1992, 9 (03) : 16 - 35
[7] EFFICIENT SIGNAL-PROCESSING ON A VLSI ARRAY
KUMAR, VKP
SASTRY, S
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1988, 35 (09): : 1103 - 1113
[8] Novel Mixed Domain VLSI Signal Processing Circuits for High Performance, Low Power and Area Penalty SOC Signal Processing
Song, Hongjiang
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2008, : 309 - 312
[9] Accuracy vs. precision in digital VLSI architectures for signal processing
Politecnico di Milano, Milano, Italy
IEEE Trans Comput, 4 (472-477):
[10] Accuracy vs. precision in digital VLSI architectures for signal processing
Alippi, C
Briozzo, L
IEEE TRANSACTIONS ON COMPUTERS, 1998, 47 (04) : 472 - 477

← 1 2 3 4 5 →