Power and Area Efficient VLSI Architectures for Communication Signal Processing

被引：0

作者：

Markovic, Dejan ^{[1
]}

Nikolic, Borivoje ^{[1
]}

Brodersen, Robert W. ^{[1
]}

机构：

[1] Univ Calif Berkeley, Berkeley Wireless Res Ctr, Berkeley, CA 94704 USA

来源：

2006 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-12 | 2006年

关键词：

Circuit synthesis; design methodology; architecture; adaptive signal processing; matrix decomposition; MIMO systems;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A methodology for VLSI realization of signal processing algorithms for wireless communications is presented that optimizes architecture for reduced power and area. When power is limited, optimal architecture represents a point on the best power-area tradeoff curve that is obtained by balancing the algorithm throughput with the power-performance tradeoff of the underlying building blocks. Architectural optimization is done in the graphical Matlab/Simulink environment, which is also used for algorithm verification. Hardware description language produced by Simulink enables algorithm emulation on the FPGA and also serves as design entry for the chip realization. This is illustrated on complex multi-dimensional algorithms such as wideband MIMO channel decoupling through singular value decomposition (SVD) using 16 sub-carriers.

引用

页码：3223 / 3228

页数：6

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