共 50 条
- [1] A buffer planning algorithm for chip-level floorplanning Science in China Series F: Information Sciences, 2004, 47 : 763 - 776
- [2] A buffer planning algorithm for chip-level floorplanning SCIENCE IN CHINA SERIES F-INFORMATION SCIENCES, 2004, 47 (06): : 763 - 776
- [4] Simultaneous floorplanning and buffer block planning ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 431 - 434
- [6] Integrating buffer planning with floorplanning for simultaneous multi-objective optimization ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 624 - 627
- [8] Noise-aware buffer planning for interconnect-driven floorplanning ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 423 - 426
- [9] Fast buffer planning and congestion optimization in interconnect-driven floorplanning ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 411 - 416
- [10] Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, : 740 - 745