A 133 MHz Radiation-Hardened Delay-Locked Loop

被引：11

作者：

Sengupta, Rajat ^{[1
,2
]}

Vermeire, Bert ^{[2
]}

Clark, Lawrence T. ^{[2
]}

Bakkaloglu, Bertan ^{[2
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

[2] Arizona State Univ, Dept Elect Comp & Energy Engn, Tempe, AZ 85281 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2010年 / 57卷 / 06期

关键词：

Charge pump; delay-locked loop (DLL); jitter phase-locked loop (PLL); single-event transients (SETs);

D O I：

10.1109/TNS.2010.2086485

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 mu m fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented.

引用

页码：3626 / 3633

页数：8

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