Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W/WNx/poly-Si gate MOSFET for high density DRAM applications

被引：3

作者：

Lim, KY ^{[1
]}

Cho, HJ ^{[1
]}

Jang, SA ^{[1
]}

Kim, YS ^{[1
]}

Oh, JG ^{[1
]}

Lee, JH ^{[1
]}

Yang, HS ^{[1
]}

Sohn, HC ^{[1
]}

Kim, JW ^{[1
]}

机构：

[1] Hynix Semicond Inc, R&D Div, Ichon Si 467701, Kyoungki Do, South Korea

来源：

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | 2005年 / 23卷 / 03期

关键词：

D O I：

10.1116/1.1897708

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have studied the effects of the gate hard mask and the gate spacer nitride film on the reliability of W/WNx/poly-Si gated devices. When the gate hard mask nitride film is used, severe degradation of the stress-induced leakage current (SILC) and the interface trap density (D-it) characteristics are observed in the large metal-oxide-semiconductor (MOS) capacitors. On the other hand, as the devices become smaller, the effects of the hard mask nitride film are relieved. The gate spacer stack plays a more critical role in the reliability of smaller devices. The oxide/nitride (ON) spacered devices exhibit better reliability m terms of SILC, D-it, threshold voltage (V-th) shift, and transconductance (G(m)) compared to those of the nitride/oxide/nitride (NON) spacered ones. These behaviors are explained by the mechanical stress of the nitride films. (c) 2005 American Vacuum Society.

引用

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页码：1036 / 1040

页数：5

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